1. Field of the Invention
The present invention relates to a radio pager and, more particularly, to a radio pager having a high-speed clock whose frequency does not interfere with a received radio frequency (RF) signal and allowing the high-frequency clock to rise in a short period of time.
2. Description of the Prior Art
Generally, a central station included in a radio paging system modulates an RF signal by a digital paging signal and sends the modulated RF signal over one of a plurality of frequency channels (e.g. 150 megahertz band; channel interval of 25 kilohertz). A radio pager has an RF section for receiving the RF signal coming in through an antenna. The RF section demodulates the RF signal to reproduce the digital paging signal while a decoder decodes the digital paging signal to output a call signal including an address signal. In response to the call signal, a reception control having a CPU as a major component thereof performs selective reception control. Specifically, the reception control determines whether or not the received address is coincident with an address assigned to the pager and stored in a ROM and, if the former is coincident with the latter, produces a tone through a speaker and/or displays a message on a display, thereby alerting the user of the pager to the call.
It is a common practice to provide the above-described radio pager with various battery saving (BS) configurations. Specifically, in a standby (SB) mode wherein a power switch is turned off or a BS mode wherein the RF signal is received intermittenly, the RF section, decoder and CPU execute digital signal processing which consumes little power in response to a low-speed clock (typically 32.768 kilohertz) fed from a low-speed clock generating circuit (or data clock generating circuit) which is included in the decoder. On the other hand, a high-speed operation is needed when a message signal should be written to a RAM (message process (MP) mode) or when a message should be displayed on the display (message display (MD) mode). In such a mode operation, the reception control and display execute digital signal processing in response to a high-speed clock (typically 2 megahertz) fed from a high-speed clock generating circuit (or operation clock generating circuit) which is included in the reception control. The high-speed clock not only aggravates the power consumption of the reception control and display but also constitutes a source of noise.
More specifically, the frequency of the high-speed clock has to be adjusted to an adequate frequency which prevents the higher harmonics of the clock from interfering with the RF signal received by the RF section or the demodulated paging signal or from disturbing the signal processing. To meet this requirement, the high-speed clock frequency is adjusted on the production line or, at the latest, after the pager has been used for the first time and before the high-speed clock is generated. However, it is likely that the circuit constant selected by the frequency adjustment is inadequate and causes the frequency-to-loop phase characteristic of the circuit to sharply change, increases the rising time of the high-speed clock, and/or practically stops the generation of the high-speed clock. In light of this, the high-speed clock generating circuit is provided with a compensation circuit for compensating the degree of circuit stability and connects a particular circuit element which minimizes the rising time of the high-speed clock to the compensation circuit. The required characteristic value of such a circuit element generally depends on the frequency of the high-speed clock. It has been customary, therefore, to select one of a plurality of frequency adjusting elements and one of the circuit elements each having an adequate characteristic and connect them to the high-speed clock generating circuit at the production stage, thereby adjusting the frequency and rising time of the high-speed clock. Selecting one adjusting element out of each of two groups of adjusting elements in matching relation to the frequency channel at the production stage is not desirable. Moreover, when the frequency channel is changed after the adjustment, the frequency and rising time of the high-speed clock have to be adjusted again by a time- and labor-consuming procedure.